1. Field of the Invention
The invention relates generally to magnetic tunnel junction (MTJ) memory devices, and, more particularly, to a system and method for determining the logic state of a memory cell in an MTJ memory device.
2. Related Art
A typical magnetic tunnel junction (MTJ) memory device includes an array of memory cells. Each of the cells is typically constructed of two layers of magnetic film, separated by a dielectric layer. The magnetization of one of the layers is alterable and the magnetization of the other layer is fixed or “pinned” in a particular direction. The magnetic film layer having alterable magnetization is typically referred to as a “data storage layer” and the magnetic film layer which is pinned is typically referred to as a “reference layer.”
Conductive traces are typically routed across the array of memory cells. These conductive traces are typically arranged in rows and columns. The conductive traces extending along the rows of the memory cells are generally referred to as “word lines” and the conductive traces extending along the columns of the memory cells are generally referred to as “bit lines.” The word lines and bit lines are typically oriented perpendicular to each other. Located at each intersection of a word line and a bit line, each memory cell stores the bit of information as an orientation of a magnetization.
Typically, the orientation of magnetization in the data storage layer aligns along an axis of the data storage layer that is commonly referred to as its “easy axis.” Typically, external magnetic fields are applied to flip the orientation of magnetization in the data storage layer along its easy axis to either a parallel or anti-parallel orientation with respect to the orientation of magnetization in the reference layer, depending on the desired logic state.
The orientation of magnetization of each memory cell will assume one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logical values of “1” and “0”, respectively. The orientation of magnetization of a selected memory cell may be changed by supplying current to a word line and a bit line crossing at the location of the selected memory cell. The currents create magnetic fields that, when combined, can switch the orientation of magnetization of the selected memory cell from parallel to anti-parallel or vice versa.
A selected magnetic memory cell is usually written by applying electrical currents to the particular word and bit lines that intersect at the selected magnetic memory cell. Typically, an electrical current applied to the particular bit line generates a magnetic field substantially aligned along the easy axis of the selected magnetic memory cell. The magnetic field aligned to the easy axis is generally referred to as a “longitudinal write field.” An electrical current applied to the particular word line typically generates a magnetic field substantially perpendicular to the easy axis of the selected magnetic memory cell.
Typically, only one selected magnetic memory cell receives both the longitudinal and the perpendicular write fields at any one time. Non-selected memory cells that are coupled to the same word line as the selected cell generally receive only the perpendicular write field. Non-selected memory cells that are coupled to the same bit line as the selected cell generally receive only the longitudinal write field.
Because the word lines and the bit lines operate in combination to switch the orientation of magnetization of the selected memory cell (i.e., to write the memory cell), the word lines and bit lines are generally referred to collectively as “write lines.” The write lines can also be used to read the logic values stored in the memory cell.
FIG. 1 is a plan view illustration of a simplified magnetic random access memory (MRAM) array, which is an exemplar MTJ memory device. The array 100 includes memory cells 120, word lines 130, and bit lines 132. The word lines 130 and bit lines 132 are referred to collectively as “write lines.” The memory cells 120 are positioned at each intersection of a word line 130 and a bit line 132. Typically, the word lines 130 and bit lines 132 are arranged in orthogonal relation to one another and the memory cells 120 are positioned between the bit lines 132 and the word lines 130.
FIGS. 2A, 2B and 2C collectively illustrate the storage of a bit of data in a single memory cell 120 of the MRAM array of FIG. 1. As illustrated in FIG. 2A, the memory cell 120 includes an active magnetic data film 122 and a pinned magnetic film 124 which are separated by a dielectric region 126. The orientation of magnetization in the active magnetic data film 122 is not fixed and can assume two stable orientations, as shown by arrow M1. In contrast, the pinned magnetic film 124 has a fixed orientation of magnetization, as shown by arrow M2. The active magnetic data film 122 rotates its orientation of magnetization in response to electrical currents applied to the write lines (i.e., the word lines 130 and bit lines 132 of FIG. 1) during a write operation to the memory cell 120. The first logic state of the data bit stored in memory cell 120 is indicated when M1 and M2 are parallel to each other, as illustrated in FIG. 2B. When M1 and M2 are parallel, a logic “1” state is stored in the memory cell 120. Conversely, a second logic state is indicated when M1 and M2 are anti-parallel to each other, as illustrated in FIG. 2C. When M1 and M2 are anti-parallel, a logic “0” state is stored in the memory cell 120. In FIGS. 2B and 2C, the dialectic region 126 has been omitted. Although FIGS. 2A, 2B and 2C collectively illustrate the active magnetic data film 122 positioned above the pinned magnetic film 124, the pinned magnetic film 124 alternatively may be positioned above the active magnetic data film 122.
The resistance of the memory cell 120 differs according to the orientations of M1 and M2. When M1 and M2 are anti-parallel (i.e., the logic “0” state), the resistance of the memory cell 120 is at its highest. On the other hand, the resistance of the memory cell 120 is at its lowest when the orientations of M1 and M2 are parallel (i.e., the logic “1” state). As a consequence, the logic state of the data bit stored in the memory cell 120 can be determined by measuring the current flowing through memory cell 120.
FIG. 3 is a simplified illustration of an MTJ array 100 having a sensing circuit 150 for measuring the sense current flowing through one cell of the array 100. The array 100 is comprised of a plurality of word lines 130 and a plurality of bit lines 132. As described with respect to FIG. 1, a memory cell 120 is formed at each intersection of a word line 130 and a bit line 132 (for simplicity only the cells on the top row are numbered, but it should be understood that a cell is formed at each intersection of word lines 130 and bit lines 132). The particular cell for which the sense current is to be measured is denoted as cell 120a. A bias voltage (Va) is applied to each of the bit lines 132 of MTJ array 100. The same bias voltage (Va) is also applied to each of the word lines 130 of MTJ array 100, with the exception of the word line that intersects cell 120a, which for clarity is denoted as word line 130a. For a symmetric array having N word lines 130 and N bit lines 132, bias voltage Va would be applied to all N of the bit lines 132 and to N−1 of the word lines 130. A second bias voltage (Vb) is applied to the word line 130a that intersects cell 120a. Typically Va>Vb and in a typical implementation, Vb is ground potential. Thus, the biasing voltage for each of the cells 120 in the array 100, with the exception of cell 120a is zero (Va−Va). The biasing voltage for cell 120a is (Va−Vb), which results in a sense current (Isc) flowing through cell 120a. Sensing circuit 150 is coupled to cell 120a by connections 151 and 152. Sensing circuit 150 measures the sense current (Isc) that flows through cell 120a as a result of the applied bias voltage (Va−Vb). The resistance (R) of the memory cell 120a at the applied bias voltage (Va−Vb) is calculated by dividing the applied bias voltage (Va−Vb) by the sense current (Isc).
The logic state of a cell in an MTJ array, such as cell 120a of FIG. 3, typically has been determined by comparing the resistance of the cell at an applied bias voltage with predetermined resistance values corresponding to the logic “1” state and the logic “0” state. However, because MTJ memory devices operate on the principle of the quantum mechanical tunnel effect, the magnitude of the sense current in a particular cell, and hence the resistance of the cell, is very highly dependent on the thickness of the dielectric layer. Because variations in dielectric thickness within an array of MTJ devices cannot be completely eliminated by current thin film process techniques, these variations can cause seemingly disproportionate variations in the magnitude of the sense current that is measured within different cells in the array. This can lead to ambiguity in determining the logic state of different cells within an array. The practical implications of this ambiguity are such that, when operating an MTJ memory device array, a large number of errors potentially may occur during the process of retrieving data if the data state of any one cell is determined by comparing that cell's resistance to some pre-determined threshold value. This occurs because the difference in resistance between cells having the same stored logic state can easily exceed the difference in resistance of one cell as its logic state is switched from a “1” to a “0”.
One way to overcome this ambiguity is to employ a data retrieval process known as a destructive read. A destructive read typically involves the following steps: (1) measuring the magnitude of sense current in a cell a first time in response to an applied voltage; (2) writing the cell to a known (previously determined) state (i.e., to a “1” or a “0”); (3) measuring the magnitude of the sense current in the cell a second time in response to a second application of the same applied voltage previously applied in step 1; and (4) determining whether the logic state of the bit in question was originally a “1” or a “0” based on the difference of the magnitude of the sense current between the first measurement and the second measurement. In addition, if the original state of the cell, as determined in step 4, is different from the state to which the cell was written during step 2, the cell must be returned to its original state by another write operation. For example, if the cell was written to a “1” during step 2, and the determination in step 4 indicated that the cell was originally a “0”, the cell must be written back to its original “0” state after the destructive read is completed. On the other hand, if the cell was written to a “1” during step 2, and the determination in step 4 indicated that the cell was originally a “1”, it would be not be necessary to perform a re-write operation to return the cell to its original state.
Although a destructive read process can be used to determine the state of a cell, this process has several significant shortcomings. Because the destructive read process requires that the cell be written to a known value and then, in some cases, written back to its original value, the destructive read process markedly increases read access time. The additional write operations also increase power consumption and may decrease the life expectancy of the cell.
The destructive read process also tends to exacerbate an undesirable condition known as half-select switching. Half-select switching may occur in an MTJ memory array having N×M cells, where N and M are greater than 1, when a write operation directed at one cell inadvertently causes an undesired change of state in another cell in the array. Ideally, a cell in an MTJ memory array will switch its logic state only when subjected to both longitudinal and perpendicular write fields, and will not switch its logic state when subjected only to either the longitudinal write field or the perpendicular write field, but not both. Thus, the magnitudes of the longitudinal and the perpendicular write fields should be sufficiently high so that the cells in the array switch their logic states only when subjected to both the longitudinal write field and the perpendicular write field. At the same time, the magnitudes of the longitudinal and the perpendicular write fields should be sufficiently low so that the cells in the array do not switch their logic states when subjected only to either the longitudinal write field or the perpendicular write field, but not both. However, in some cases a cell in the array may change its state even though it is only subjected to either the longitudinal write field or the perpendicular write field, but not both. This undesirable switching of a magnetic memory cell that receives only the longitudinal or the perpendicular write field is commonly referred to as half-select switching.
Half-select switching can, if present, cause catastrophic errors when operating an MTJ memory array. For example, an attempt to switch the logic state of a first cell in an array from “0” to “1” may have the inadvertent and undesired effect of erroneously changing the logic state of a second cell in the array from “0” to “1” as well. Although the problem of half-select switching may be mitigated by magnetic process engineering improvements, it is unlikely to be totally eliminated. Therefore, in order to minimize the potential for half-select switching, it is preferable to keep the number of write operations to a minimum. However, the destructive read process requires at least one extra write operation for each cell being read, and potentially two extra write operations if the cell must be re-written to its original state. Therefore, the destructive read process increases the likelihood that half-select switching will occur.
Therefore, there is a need for a system and method for determining the logic state of a cell in a magnetic tunnel junction (MTJ) memory device that overcomes the deficiencies and inadequacies stated above.